Elevating IoT with the World’s Lowest Power Platform-on-a-Chip.
About the Company
InnoPhase IoT is a vibrant and innovative company where brilliant minds from diverse backgrounds come together, driven by the values of working smart and celebrating successes. Focused on cutting-edge technology within a small company environment, InnoPhase IoT offers an exciting playground for those eager to learn and experience different aspects of work beyond routine tasks. The company specializes in ultra-low-power wireless IoT solutions for home, building, industrial automation, and wearables, pushing the boundaries of innovation in the semiconductor space.
About the Role
The Physical Design Principal Engineer will take full ownership of the SoC implementation and verification flow from RTL-to-GDS. This includes floorplanning, place and route, clock tree synthesis (CTS), static timing analysis (STA), power and signal integrity verification (PV/EMIR/Noise/SigEM), and signoff for low-power SoCs. The engineer will collaborate closely with the SoC design team to drive architectural feasibility, develop timing, power, and area targets, and explore design trade-offs to deliver top-tier semiconductor products for a leading fabless wireless platform company.
Key Responsibilities
- Complete the entire physical implementation of blocks and chip level designs
- Perform synthesis, floorplanning, power delivery planning, place & route, timing closure ECOs, and physical verification tasks (DRC/LVS/ERC/ANTENNA cleanup)
- Collaborate with SoC design team to evaluate architectural feasibility and set timing, power, and area design targets
- Analyze floorplan quality, clock tree structures, and place & route results
- Conduct signal EM/noise and power IR/EM analysis and implement fixes
- Perform timing verification and signoff
- Complete full physical verification and signoff of the chip
- Implement design changes to meet timing and power goals
- Utilize Perl and TCL scripting for automation and flow improvements
Required Skills
- Master’s degree (or higher) in Electrical or Computer Science Engineering with 10+ years of industry experience, or Bachelor’s degree with 15+ years
- Extensive experience in power/ground grid design, partitioning, timing ECO implementation, and physical verification
- Proficient in full SoC implementation and verification flow from RTL-to-GDS, including floorplanning, place and route, CTS, and layout verification signoff for low-power SoCs
- Hands-on experience with netlist (or RTL) to GDS physical implementation
- Deep knowledge of major EDA tools and design flows
- Strong Cadence tool expertise
- Experience with TSMC N22 technology node or below
- Proven track record in chip integration and signoff
- Programming experience with Perl and TCL
Preferred Qualifications
- Strong background in low-power implementation methodology
- Experience in advanced timing signoff methodologies
- Knowledge of Design-for-Test (DFT) techniques such as BSCAN, MBIST, SCAN, and their impact on physical design
- Ability to independently complete netlist-to-GDS place & route and signoff tasks
- Demonstrated success in multi-million gate design production tapeouts