MIPS
Freedom to Innovate Compute
About the Company
A fast-growing CPU IP team focused on developing next-generation chips for Physical AI, Networking, and custom compute platforms. Known for a lean, highly technical culture, the team is dedicated to accelerating innovation across all levels of the semiconductor design stack.
About the Role
The EDA / CAD Engineer will lead the development and scaling of front-end design automation flows and continuous integration/continuous orchestration (CI/CO) infrastructure. This position bridges digital design, tools engineering, and DevOps, supporting the full RTL lifecycle from code check-in through synthesis readiness. Close collaboration with RTL and verification engineers is essential to optimize developer efficiency and flow stability.
Key Responsibilities
- Develop, implement, and maintain automation flows for simulation, regression, and code coverage
- Manage RTL parameterization, linting, configuration, and synthesis processes
- Oversee batch job execution and compute load balancing with tools such as LSF or RDMA
- Build and maintain CI/CO infrastructure integrating sanity checks and regression triggers
- Automate RTL check-in workflows using Git and ensure traceability from code check-in to test reporting
- Collaborate cross-functionally to enhance the usability and robustness of flow tools
- Develop internal automation tools and scripts using Python, Perl, Ruby, or similar languages
- Own documentation, monitoring, and debugging infrastructure for design automation flows
Minimum Qualifications
- 10+ years of experience in EDA, CAD engineering, or RTL automation workflows
- Proficiency in scripting languages including Python, Perl, Ruby, and Bash
- Solid coding skills in C or C++
- Advanced UNIX/Linux skills, including shell scripting, sed, awk, and regex expertise
- Experience with job schedulers like LSF, RDMA, or SLURM for flow automation
- Familiarity with Git and managing Jira workflows triggered by source control events
- Bachelor’s degree or higher in Computer Science, Electrical Engineering, or related discipline
Preferred Qualifications
- Understanding of RTL design and verification processes
- Experience with SystemVerilog and UVM methodologies
- Familiarity with CI tools such as Jenkins, GitLab CI, or GitHub Actions
- Knowledge of major EDA toolchains (Synopsys, Cadence, Siemens)
- Database development experience
- Strong grasp of modern digital design methodology from specification through tape-out
What You’ll Get
- Influence in a small, high-impact engineering team
- Opportunity to design and scale automation infrastructure from the ground up
- Competitive salary plus stock grants
- Flexible work hours and a remote-friendly environment
- A fast-paced culture valuing autonomy and engineering excellence