Principal Engineer with Perl

About InnoPhase IoT

At InnoPhase IoT, we believe in the power of diverse talent, smart work, and celebrating achievements. If you’re someone who thrives in a dynamic environment surrounded by intelligent and passionate individuals, this is the place for you. Whether you’re excited by groundbreaking technology in a fast-paced startup setting or eager to expand your skills across multiple areas—not just repeat the same tasks—InnoPhase IoT offers a vibrant and engaging environment to grow and innovate.

We’re on the lookout for people who strive for excellence and impact. You can work anywhere if you’re good—but if you’re great, we invite you to join us and be part of something exceptional.

Role Overview: Physical Design Principal Engineer

In this role, you will lead the full SoC physical design and verification cycle, handling everything from RTL to GDSII. Your responsibilities will cover floorplanning, placement and routing, clock tree synthesis (CTS), static timing analysis (STA), and signoff checks including power integrity (IR), electromigration (EM), noise analysis, and physical verification for ultra-low-power SoCs. You’ll be part of a high-performing team within a fabless semiconductor company, known for its advanced wireless radio solutions designed for extremely low-power applications.

Location: San Diego or San Jose, California

Key Responsibilities

• Own the complete physical design process at both block and full-chip levels

• Perform synthesis, floorplanning, power grid design, placement and routing, timing and noise analysis, and all aspects of physical verification (LVS/DRC/ERC/ANTENNA)

• Partner with SoC designers to define architecture feasibility, power/timing/area goals, and help refine RTL for better implementation outcomes

• Evaluate floorplan quality, custom clock tree structures, and placement efficiency

• Execute timing ECOs to ensure closure and performance targets

• Analyze and resolve Signal EM, Power IR, and noise issues

• Drive design to tapeout with full verification and signoff

• Ensure design compliance and robustness through thorough quality checks

Minimum Qualifications

• Master’s degree in Electrical or Computer Engineering and 10+ years of relevant experience, or a Bachelor’s degree with 15+ years of experience

• Hands-on expertise in full SoC physical design and verification, from RTL through GDS

• In-depth knowledge of power grid planning, partitioning, timing closure, and physical signoff

• Extensive experience with industry-standard EDA tools (especially Cadence tools)

• Practical experience in physical implementation for netlist/RTL-to-GDS flows

• Familiarity with TSMC N22 or smaller process technologies

• Strong scripting skills in Perl or TCL

• Proven success in chip integration and signoff

Preferred Qualifications

• Deep knowledge of low-power design methodologies

• Expertise in advanced timing signoff and constraints management

• Understanding of Design for Test (DFT), including scan chains, MBIST, and boundary scan, and how they affect physical design

• Ability to independently complete P&R and signoff tasks

• Experience with multiple successful tapeouts of multi-million gate SoCs

Why InnoPhase IoT?

We’re not just about technology—we’re about people. InnoPhase IoT is transforming wireless IoT by developing ultra-low power solutions that enable smarter automation across homes, buildings, industries, and wearables. Our culture fosters innovation, encourages collaboration, and celebrates breakthroughs. We’re proud of our inclusive and growth-driven workplace, where every team member is encouraged to make a difference and shape the future of connected devices.

We believe that a company succeeds only when its people do. That’s why we emphasize recognition, motivation, and authenticity in everything we do. At InnoPhase IoT, your contributions matter. You’ll be heard, supported, and empowered to grow—not only as a professional but as a part of our shared mission.